The number of possible addresses with 3-lines is 2 3=8. For instance, let us not mind the source of address and consider three address lines through which addresses are obtained. This is achieved by using AND Gate with a suitable number of inputs as that of the address lines and some Inverters. In order to enable the chip with a particular address, this chip selection technique is used. ![]() The address lines of the processor contain the address of the particular peripheral. In large Digital circuits or multiple input/output systems, the central processor has to exchange data with its peripherals. ![]() This method can be employed to reduce the number of communication channels required in the processor, unless data from all the channels is required at a time.Ħ.9 Chip Selection / Stage Selection Technique Tri-state Output Buffer Gate Operationĭata coming from one of the multiple channels can be selected using these buffers. IC packages with 6 Buffers are available. This property is useful in the input selection. Outputs of two or more buffers can be connected together without the problem of short-circuiting. If the enable input is not active, then the output is in High impedance state or the Tri-state. The output of this gate is same as that of its input if the buffer is enabled. Buffers in Proteus 6.8 Buffers with Tri-state Output Also, this is used to increase the propagation delay. This is generally used to strengthen weak signal in any part of the circuit. It is a single input and single output gate. The output of this gate is same as that of its input. The output of this gate is opposite to its input. XOR Gates with inputs up to 9 are available for simulation. Two input X-OR gate function is similar to Two-Way switches in the electrical switchboards. If there is an Odd number of HIGH Inputs, then the output is HIGH. NAND Gates with inputs up to 13 are available for simulation. any logic can be derived using NAND gates. NAND Gate is one of the two universal gates i.e. The output is LOW only when all the inputs are HIGH. If any one of the inputs of NAND Gate is LOW then the output of NAND Gate is HIGH. any logic can be derived using NOR gates.NOR Gates with inputs up to 8 are available for simulation. NOR Gate is one of the two universal gates i.e. The output is HIGH only when all the inputs are LOW. If any one of the inputs of NOR Gate is HIGH then the output of NOR Gate is LOW. However, for hardware implementation, the designers have to confirm their availability in the market from time-to-time AND Gate operation 6.3 NOR Gate If the inputs are applied manually using switches, the inputs must be pulled down for active high inputs and pulled up for active low inputs.ĪND Gates with inputs up to 8 are available for simulation. If all the inputs of AND Gate are HIGH, then the output of AND Gate is HIGH. OR Gates with inputs up to 12 are available for simulation.However, for hardware implementation, the designer has to confirm their availability in the market from time-to-time OR Gate operation 6.2 AND Gate If the inputs are applied manually using switches, the inputs must be pulled down for active high inputs and pulled up for active low inputs. If any one of the inputs of OR Gate is HIGH, then the output of OR Gate is HIGH. Right-click on the component and select edit properties. One can view the hidden pins of an IC in its properties tab.All the power pins like Vcc and GND of the ICs are internally connected and those pins are hidden.Use Bus mode of wiring for connections if there are too many ICs or if the wiring is untidy.While analyzing circuits with Oscilloscope, set the channels to DC mode.It is advised to set model type of resistors in the resistor properties to Digital while using them with Digital ICs in the simulation software. ![]() Do not connect LEDs directly to the outputs even for simulation purpose, as it may lead to incorrect operation of the circuit due to shifting of voltage levels.
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